Reticle for creating resist-filled vias in a dual damascene process

ABSTRACT

An apparatus, system and method for fabricating a wafer utilizing a dual damascene process are described. A wafer-in-process, having conductive plugs within a first dielectric layer, a hard mask over the first dielectric layer, vias in a second dielectric layer which overlies the hard mask, and a photoresist material within the vias is further processed by a photolithographic device having transparent portions and radiant energy inhibiting portions. The photolithographic device is registered to the wafer-in-process to prevent radiant energy from being directly transmitted into the photoresist material overlaying the vias. This prevents the exposure of a portion of the photoresist material at a lower portion of the vias, thus protecting the hard mask layer and/or the conductive plugs from damage during a subsequent etching process. The exposed photoresist material is then removed.

FIELD OF THE INVENTION

[0001] The present invention generally relates to semiconductorfabrication. More particularly, the present invention relates to aphotolithographic device adapted to protect electrical contact portionsof a wafer-in-process, as well as an intermediate wafer product createdduring a dual damascene process.

BACKGROUND

[0002] In the manufacture of integrated circuits (ICs),microlithographic techniques are used to pattern one or more layers ofconductive circuitry on a wafer. Referring to the wafer 10 shown inFIGS. 1-2, one typical microlithography patterning technique is a dualdamascene process, which begins with the formation of openings 19 in afirst dielectric material structure 18. A conductive material is thendeposited over the dielectric structure 18 and within the openings 19. Achemical mechanical polish (CMP) is used to ablate the conductivematerial from a top surface of the dielectric structure, leaving plugsof conductive material 20 within the openings 19.

[0003] A hard mask layer 14 and a second dielectric material structure12 are respectively positioned over the first dielectric structure 18.Vias 16 are formed in the second dielectric structure 12 and the hardmask layer 14, the vias 16 extending to the conductive plugs 20. Aphotoresist material is then deposited over the second dielectricstructure 12 and within the vias 16. With a photolithographic device,such as a semiconductor mask or a reticle, the photoresist material isexposed and then developed. Specifically, the wafer-in-process is etchedto create a large open area. The remaining photoresist is then removed,and a conductive material 62 is deposited within the vias 16 and overthe dielectric structure. A CMP of the conductive material may beperformed to prepare the wafer 10 for further processing. The wafer 10thus formed may be incorporated within a semiconductor device, such as amemory cell in a DRAM.

[0004] A disadvantage in the above-described method is that all of thephotoresist material in the vias 16 is exposed and developed. Thisuncovers the electrical contact portions adjacent to the hard mask layer14 (i.e., the conductive plugs 20) during the subsequent etching of thewafer-in-process to create the large open area. This may lead topossible damage of the hard mask layer 14 and/or the conductive plugs20.

[0005] While seen in the fabrication of all wafers, this disadvantage ismore prevalent when large circuitry is to be formed, such as in a largemetal bus or a large bonding pad. Using a conventional photolithographicdevice for developing the photoresist material in wafers, the depth offocus (DOF) of the radiant energy is greater than the depths of the vias16, and hence all the photoresist material within the vias 16 may beexposed and developed, or removed.

[0006] There exists a need for a photolithographic device which protectsthe electrical contacts of wafers-in-process during subsequent waferfabrication processes.

SUMMARY

[0007] An embodiment of the present invention provides aphotolithographic device adapted for developing a portion of photoresistmaterial on a wafer-in-process including vias within a dielectric layeroverlain by the photoresist material. The device includes a radiantenergy transparent portion and radiant energy blocking portions. Theblocking portions are registered to the wafer-in-process to preventdirect radiant energy transmission to the photoresist material directlyoverlaying the vias.

[0008] Another embodiment of the present invention provides a system forfabricating a wafer including a source of radiant energy and aphotolithographic device positioned between the source of radiant energyand a wafer-in-process including vias within a dielectric layer overlainwith a photoresist material. The photolithographic device has a radiantenergy transparent portion and radiant energy blocking portions. Theblocking portions are registered to the wafer-in-process to preventdirect radiant energy transmission to the photoresist material directlyoverlaying the vias.

[0009] Another embodiment provides a method of fabricating a waferincluding a plurality of conductive plugs in a first dielectric layeroverlain by a hard mask layer and a second dielectric layer. The methodincludes forming vias in the second dielectric layer, each via extendingto a corresponding conductive plug, applying a photoresist material tofill the vias and cover the second dielectric layer, and exposing aportion of the photoresist material so as to leave unexposed a secondportion of the photoresist material located at a lower portion of thevias. The exposing includes using a photolithographic device which isadapted to prevent direct transmission of radiant energy to thephotoresist material directly overlaying the vias.

[0010] Another embodiment provides a wafer-in-process including a firstdielectric layer, at least one conductive plug within said firstdielectric layer, a hard mask layer positioned atop said firstdielectric layer, a second dielectric layer over said hard mask layer,at least one via extending through said second dielectric layer and saidhard mask layer to said conductive plug, and photoresist materialpositioned only at a portion of said via adjacent said hard mask layer

[0011] The foregoing and other objects, features and advantages of theinvention will be more readily understood from the following detaileddescription of preferred embodiments of the invention, which is providedin connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a top view of part of a portion of a wafer constructedin accordance with an embodiment of the present invention.

[0013]FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

[0014]FIG. 3 is a top view of a photolithographic device constructed inaccordance with an embodiment of the present invention.

[0015]FIG. 4 is a cross-sectional view of the photolithographic deviceof FIG. 3 is use to form the wafer of FIG. 1.

[0016]FIG. 5 is another cross-sectional view of the formation of thewafer of the FIGS. 1, 2, and 4.

[0017] FIGS. 6A-L are a flow diagram illustrating the wafer fabricationprocess depicted in FIGS. 1, 2, 4 and 5.

[0018]FIG. 7 is a flow diagram illustrating the wafer fabricationprocess depicted in FIGS. 1, 2 and 4-6.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0019] Referring to FIGS. 1-2, there is illustrated a portion of a wafer10. FIGS. 1 and 2 show an upper portion of the wafer 10, which is builton a supporting substrate 70. The substrate 70 may have electronicdevices or regions fabricated therein. The wafer 10 has a firstdielectric layer 18, upon which is located a hard mask layer 14.Positioned atop the hard mask layer 14 is a second dielectric layer 12.Conductive plugs 20 formed of a conductive material fills openings 19 inthe first dielectric layer 18. The conductive plugs 20 may connect withan active region or another conductor within the substrate 70. Vias 16extend from a top surface of the second dielectric layer 12 to a bottomsurface of the hard mask layer 14. Conductive material fills each via 16and contacts a corresponding conductive material plug 20.

[0020] The dielectric layers 12, 18 may be formed of any suitabledielectric material, such as, for example, borophosphosilicate glass(BPSG), tetra ethyl orthosilane (TEOS) or plasmas enhanced TEOS(PETEOS). The conductive material 20 may be formed of a suitablyconductive material, such as a metal. Suitable metals include copper,aluminum, gold, silver, titanium and the like. The hard mask layer 14 isformed of a material resistant to certain etchants. Preferably, the hardmask layer 14 is formed of silicon nitride. The wafer-in-process ischemical mechanical polished to prepare the surface for furtherprocessing.

[0021] A conventional process has been illustrated in FIGS. 1 and 2.FIGS. 3-5 illustrate the formation of the wafer 10 in accordance with anembodiment of the present invention. FIG. 3 illustrates aphotolithographic device 30, such as a semiconductor mask or reticle,which includes a transparent substrate 32 and radiant energy inhibitingportions 34. The transparent substrate 32 is formed of quartz, glass, orany other material transparent to radiant energy. The inhibitingportions 34 are formed of a material which will prevent passage ofradiant energy, such as chromium or other like opaque materials.Alternatively, a translucent or semi-opaque material may be used toinhibit the passage of radiant energy.

[0022]FIG. 4 shows the FIG. 2 structure at the point where a photoresistlayer 22 has been applied to the dielectric layer 12 which has the vias16 formed therein. As shown in FIG. 4, a radiant energy source 50projects radiant energy toward the photolithographic device 30, whichfor simplicity's sake will hereinafter be called a reticle 30. A portion40 of the radiant energy is inhibited by the inhibiting portions 34 fromprojecting onto and exposing portions of the photoresist material 22while another portion 42 of the radiant energy extends through thereticle 30. The reticle 30 is registered to the wafer-in-process suchthat each inhibiting portion 34 obstructs the radiant energy portion 40from direct transmission to the photoresist material 22 overlaying, andpositioned in, a corresponding via 16.

[0023] By inhibiting direct projection of radiant energy to portions ofthe photoresist material 22 within or above the vias 16, a lower portion26 of the photoresist material 22 remains unexposed, while an upperportion 24 of the photoresist material 22 still becomes exposed and maythen be removed (FIG. 5). The lower portions 26 of the photoresist layer22 protect the hard mask layer 14 and the conductive plugs 20 during asubsequent processing step performed on the wafer 10 (described indetail below). Strategic placement of the inhibiting portions 34 on thereticle 30 prevents the depth of focus (DOF) of the radiant energy fromextending beyond the depth of the vias 16, allowing the lowerphotoresist portions 26 to remain in a lower quadrant of the vias 16.Preferably, the unexposed lower photoresist portions 26 should protectat least the conductive plugs 20, and more preferably also protect thehard mask layer 14. Thus, more preferably the unexposed lowerphotoresist portions 26 should extend from the conductive plugs 20beyond the hard mask layer 14.

[0024] With reference to FIG. 4, by directing radiant energy through aproperly registered reticle 30, an exposure pattern emerges on thewafer-in process in which the photoresist material 22 directly above thevias 16 has a reduced exposure relative to other portions of thephotoresist material 22. Specifically, in the photoresist material 22surrounding the vias 16, the normalized intensity (exposure/time) isabout 0.90 to about 1.00. However, because of the inhibiting or opaqueportions 34 directly blocking radiant energy from the vias 16, thenormalized intensity at the photoresist material 22 overlaying the vias16 is about 0.58 to about 0.34.

[0025] FIGS. 6-7 illustrate a method of fabricating the wafer 10 inaccordance with the present invention. Step 100 (FIGS. 6A, 7) is an etchof the first dielectric layer 18. Radiant energy projects through atransparent substrate 31 of a photolithographic device 29 onto aphotoresist layer 52 on the first dielectric layer 18. Opaque orinhibiting portions 33 prevent radiant energy from extending to someparts of the photoresist layer 52. The radiant energy may be anysuitable form capable of developing the photoresist layer 52, as is wellknown in the art. The radiant energy extending through the transparentsubstrate 31 forms openings in the photoresist layer 52. These openingsin the photoresist layer 52 are in turn used in the etching of the firstdielectric layer 18 to form the openings 19 therein (FIG. 6B).

[0026] After formation of the openings 19 in the first dielectric layer18, conductive material 21 is deposited within the openings 19 and overthe first dielectric layer 18 at step 105 (FIG. 6C). Conductive plugs 20are then formed at step 110 (FIG. 6D). Preferably, a chemical mechanicalpolish (CMP) is performed on the conductive material 21 overlaying thefirst dielectric layer 18 to ablate that portion of the material 21,leaving behind the conductive plugs 20.

[0027] The hard mask layer 14 is then deposited over the firstdielectric layer 18 and the conductive plugs 20 at step 115 (FIG. 6E).The second dielectric layer 12 is then deposited on the hard mask layer14 at step 120 (FIG. 6F).

[0028] The vias 16 are formed in the second dielectric layer 12 and thehard mask layer 14 at step 125 (FIGS. 6F, 6G). Specifically, radiantenergy is projected through transparent portions 231 of aphotolithographic device 229 onto a photoresist layer 54 to exposeportions of it. The layer 54 is then developed and openings therein areused to etch the second dielectric layer 12 and the hard mask 24 to formthe vias 16. Radiant energy is inhibited from projecting through part ofthe device 229 to the wafer-in-process due to the positioning of opaqueor inhibiting portions 233. The device 229 is registered to thewafer-in-process so as to position the openings in the photoresist layer54 to form each via 16 to contact a corresponding conductive plug 20.

[0029] The vias 16 are filled with the photoresist material 22, whichextends over a top surface of the second dielectric layer 12, at step130 (FIG. 6H). As noted above, the photoresist material 22 includes ashallow portion 24 and a deep portion 26.

[0030] At step 135, a portion of the photoresist material 22 is exposed(FIGS. 6H, 61). Specifically, the radiant energy 42 projects through thetransparent portions 32 of a photolithographic device 30. The device 30includes the inhibiting or opaque portions 34 which inhibit the radiantenergy 42 from directly extending through the device 230 to thewafer-in-process. The device 30 differs from the device 229 in that theopaque portions 34 are positioned to inhibit radiant energy fromdirectly reaching the vias 16, while the opaque portions 233 arepositioned out of a direct line with the vias 16 and the radiant energy.In other words, the device 30 is the inverse of the device 229. Theexposed portions of the photoresist 22 are removed, leaving an openspace 60 and some remaining unexposed deep portions 26 of thephotoresist 22 in the vias 16.

[0031] After removing the exposed portions of the photoresist 22, thewafer-in-process is etched at step 140 (FIG. 6J). Specifically, the topsurface of the second dielectric layer 12 is etched to increase thesurface area of the open space 60. After such processing, the remainingdeep portions 26 of the photoresist material 22 are removed at step 145.

[0032] The vias 16 and the open space 60 are then filled at step 150with the conductive material 62 (FIG. 6K). A portion of the conductivematerial 62 is ablated through chemical mechanical polishing at step 155(FIG. 6L) to prepare the surface for further processing.

[0033] The described embodiments provide protection for the conductiveplugs 20 and the hard mask layer 14 during etching of the open space 60by the simple expedient of leaving some photoresist 22 at the bottom ofthe vias 16 when photoresist patterning the area for etching the seconddielectric layer 12 to produce the open space 60.

[0034] While the invention has been described in detail in connectionwith the preferred embodiments known at the time, it should be readilyunderstood that the invention is not limited to such disclosedembodiments. Rather, the invention can be modified to incorporated anynumber of variations, alterations, substitutions or equivalentarrangements not heretofore described, but which are commensurate withthe spirit and scope of the invention. For example, while portions 33,34, and 233 are described as opaque, translucent, semi-opaque or likematerials capable of keeping the radiant energy DOF less than the depthof the vias 16 may be used. Accordingly, the invention is not to be seenas limited by the foregoing description, but is only limited by thescope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A photolithographic device adapted for exposinga portion of photoresist material on a wafer-in-process, said wafer-inprocess including vias within a first dielectric layer and a photoresistmaterial provided over said first dielectric layer and within said vias,said device comprising: a radiant energy transparent portion; andradiant energy blocking portions, said blocking portions beingregistered to said wafer-in-process to prevent direct radiant energytransmission to the photoresist material directly overlaying the vias.2. The photolithographic device of claim 1, wherein the device comprisesa reticle.
 3. The photolithographic device of claim 1, wherein thedevice comprises a semiconductor mask.
 4. The photolithographic deviceof claim 1, wherein the blocking portions are positioned between thetransparent portion and the wafer-in-process.
 5. The photolithographicdevice of claim 1, wherein said device produces a normalized intensityof the radiant energy on the photoresist material directly overlayingthe vias is in the range of about 0.58 to about 0.34.
 6. Thephotolithographic device of claim 1 for use in preparing thewafer-in-process having a second dielectric layer with a plurality ofconductive portions therein, a hard mask layer overlaying said seconddielectric layer and being overlain by said first dielectric layer, saidvias within said first dielectric layer each extending through said hardmask layer to a corresponding said conductive portion.
 7. Thephotolithographic device of claim 6, wherein said portion of photoresistmaterial being exposed is removed, leaving behind a layer of unexposedphotoresist material at the bottom of said vias.
 8. A system forfabricating a wafer comprising: a source of radiant energy; and aphotolithographic device adapted for exposing a portion of photoresistmaterial on a wafer-in-process and positioned between said source ofradiant energy and said wafer-in-process, said wafer-in-processincluding vias within a dielectric layer and a photoresist materialoverlaying said dielectric layer and provided within said vias, saidphotolithographic device comprising: a radiant energy transparentportion; and radiant energy blocking portions, said blocking portionsbeing registered to the wafer-in-process to prevent direct radiantenergy transmission to the photoresist material directly overlaying thevias.
 9. The system of claim 8, further comprising a substratesupporting said dielectric layer.
 10. The system of claim 8, wherein theblocking portions are positioned between the transparent portion and thewafer-in-process.
 11. The system of claim 8, wherein said deviceproduces a normalized intensity of the radiant energy on the photoresistmaterial directly overlaying the vias is in the range of about 0.58 toabout 0.34.
 12. The system of claim 8, wherein said photolithographicdevice comprises a reticle.
 13. The system of claim 8, wherein saidphotolithographic device comprises a semiconductor mask.
 14. The systemof claim 8 for use in preparing the wafer-in-process having a seconddielectric layer with a plurality of conductive portions therein, a hardmask layer overlaying said second dielectric layer and being overlain bysaid first dielectric layer, said vias within said first dielectriclayer each extending through said hard mask layer to a correspondingsaid conductive portion.
 15. The system of claim 14, wherein saidportion of photoresist material being exposed is removed, leaving behinda layer of undeveloped photoresist material at the bottom of said vias.16. A wafer-in-process comprising: a first dielectric layer having atleast one opening extending therethrough in which is positionedconductive material; a hard mask layer overlaying said first dielectriclayer; a second dielectric layer overlaying said hard mask layer, saidsecond dielectric layer including at least one via extending throughsaid hard mask layer to said conductive material; and photoresistmaterial positioned only at a lower portion of said via and coveringsaid conductive material, said photoresist material serving to protectsaid conductive material during steps of fabricating saidwafer-in-process.
 17. The wafer-in-process of claim 16, wherein saidphotoresist material extends above said hard mask layer in said via. 18.The wafer-in-process of claim 17, wherein said hard mask layer comprisessilicon nitride.
 19. The wafer-in-process of claim 18, wherein saidfirst dielectric layer includes a plurality of openings, each saidopening having conductive material therein, and said second dielectriclayer includes a plurality of vias, each said via extending to acorresponding said opening.
 20. A method of fabricating a wafer from awafer-in-process, said wafer including a plurality of conductive plugsin a first dielectric layer, a hard mask layer overlaying said firstdielectric layer and being overlain by a second dielectric layer, saidmethod comprising: forming vias in the second dielectric layer and saidhard mask layer, each said via extending to a corresponding conductiveplug; applying a photoresist material to fill the vias and cover thesecond dielectric layer; and exposing a first portion of the photoresistmaterial within an upper portion of said said vias while leavingunexposed a second portion of the photoresist material located at alower portion of the vias.
 21. The method of claim 20, wherein saidexposing includes using a photolithographic device adapted to preventdirect transmission of radiant energy to the photoresist materialdirectly overlaying the vias.
 22. The method of claim 21, wherein saidexposing comprises registering the photolithographic device to the waferto prevent said direct transmission of radiant energy to the photoresistmaterial directly overlaying the vias.
 23. The method of claim 22,wherein the photolithographic device, which includes a radiant energytransparent portion and radiant energy blocking portions, is registeredto position each radiant energy blocking portion over a correspondingvia.
 24. The method of claim 23, wherein the photolithographic device isregistered and said blocking portions are located to allow a normalizedintensity of the radiant energy on the photoresist material directlyoverlaying the vias of no more than about 0.58.
 25. The method of claim23, wherein the photolithographic device is registered and said blockingportions are located to allow a normalized intensity of the radiantenergy on the photoresist material directly overlaying the vias in arange of about 0.58 to about 0.34.
 26. The method of claim 20, furthercomprising removing said exposed first portion of the photoresistmaterial.
 27. The method of claim 26, further comprising, after removingsaid first portion of the photoresist material, etching an upper portionof the second dielectric layer.
 28. The method of claim 27, furthercomprising removing the second portion of the photoresist material fromthe vias.
 29. The method of claim 28, further comprising depositingconductive material in the vias.
 30. The method of claim 20, furthercomprising, prior to forming the vias, etching the first dielectriclayer to form openings.
 31. The method of claim 30, further comprisingdepositing conductive material in the openings to form the conductiveplugs.
 32. The method of claim 31, further comprising depositing thehard mask layer on the first dielectric layer.
 33. The method of claim32, further comprising depositing the second dielectric layer on thehard mask layer.
 34. A method of fabricating a wafer from awafer-in-process, said wafer including a plurality of conductive plugsin a first dielectric layer, a hard mask layer overlaying the firstdielectric layer, and a second dielectric layer overlaying the hard masklayer, said method comprising: forming vias in the second dielectriclayer and the hard mask layer, each said via extending to acorresponding conductive plug; applying a photoresist material to fillthe vias and cover the second dielectric layer; exposing a first portionof said photoresist material through a photolithographic device adaptedto prevent direct transmission of radiant energy to the photoresistmaterial directly overlaying the vias while leaving unexposed a secondportion of the photoresist material located at a lower portion of thevias; and developing said first portion of the photoresist material. 35.The method of claim 34, wherein the photolithographic device, whichincludes a radiant energy transparent portion and radiant energyblocking portions, is registered to position a radiant energy blockingportion over a corresponding via.
 36. The method of claim 35, whereinthe photolithographic device is registered and said blocking portionsare located to allow a normalized intensity of the radiant energy on thephotoresist material directly overlaying the vias of no more than about0.58.
 37. The method of claim 36, wherein the photolithographic deviceis registered and said blocking portions are located to allow anormalized intensity of the radiant energy on the photoresist materialdirectly overlaying the vias in a range of about 0.58 to about 0.34. 38.The method of claim 37, further comprising, after developing said firstportion of the photoresist material, etching an upper portion of thesecond dielectric layer.
 39. The method of claim 38, further comprisingremoving the second portion of the photoresist material from the vias.40. The method of claim 39, further comprising depositing conductivematerial in the vias.
 41. The method of claim 34, further comprising:prior to forming the vias, etching the first dielectric layer to formopenings; and depositing conductive material in the openings to form theconductive plugs.
 42. The method of claim 41, further comprisingdepositing the hard mask layer on the first dielectric layer.
 43. Themethod of claim 42, further comprising depositing the second dielectriclayer on the hard mask layer.